MT41J64M16LA-187E:B

Product Summary

The DDR3 SDRAM MT41J64M16LA-187E:B uses a double data rate architecture to achieve high-speed operation. The double data rate architecture of MT41J64M16LA-187E:B is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) of MT41J64M16LA-187E:B is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.

Parametrics

MT41J64M16LA-187E:B absolute maximum ratings: (1)VDD supply voltage relative to VSS, VDD: -0.4 to 1.975V; (2)VDD supply voltage relative to VSSQ, VDDQ: –0.4 to 1.975V; (3)Voltage on any pin relative to VSS, VIN, VOUT: -0.4 to 1.975V; (4)Operating case temperature, TC: 0 to 95℃; (5)Storage temperature, TSTG: –55 to 150℃.

Features

MT41J64M16LA-187E:B features: (1)VDD = VDDQ = +1.5V ±0.075V; (2)1.5V center-terminated push/pull I/O; (3)Differential bidirectional data strobe; (4)8n-bit prefetch architecture; (5)Differential clock inputs (CK, CK#); (6)8 internal banks; (7)Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals; (8)CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11; (9)POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2; (10)CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK; (11)Fixed burst length (BL) of 8 and burst chop (BC) of 4; (12)Selectable BC4 or BL8 on-the-fly (OTF); (13)Self refresh mode; (14)Tc of 0℃ to 95℃; (15)Clock frequency range of 300 to 800 MHz; (16)Self refresh temperature (SRT); (17)Automatic self refresh (ASR); (18)Write leveling; (19)Multipurpose register; (20)Output driver calibration.

Diagrams