(Hong Kong)
Product Summary
The CY7C4291V-15JXC is a high-speed, low-power FIFO memory with clocked read and write interfaces. The CY7C4291V-15JXC has an output-enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. The CY7C4291V-15JXC provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full.
Parametrics
CY7C4291V-15JXC absolute maximum ratings: (1)Storage temperature:–65℃ to +150℃; (2)Ambient temperature with power applied:–55℃ to +125℃; (3)Supply voltage to ground potential:–0.5 V to +3.6 V; (4)DC voltage applied to outputs:–0.5 V to VCC + 0.5 V; (5)Output current into outputs (LOW):20 mA; (6)Static discharge voltage:> 2001 V(per MIL-STD-883, Method 3015) ; (7)Latch-up current:> 200 mA.
Features
CY7C4291V-15JXC features: (1)3.3 V operation for low-power consumption and easy ; (2)integration into low-voltage systems; (3)High-speed, low-power, first-in first-out (FIFO) memories; (4)128 K × 9; (5)0.35-micron CMOS for optimum speed or power; (6)High-speed 100-MHz operation (10-ns read/write cycle times); (7)Low power: ICC = 25 mA, ISB = 4 mA; (8)Fully asynchronous and simultaneous read and write operation; (9)Empty, Full, and programmable Almost Empty and Almost Full status flags; (10)Output-enable (OE) pin; (11)Independent read- and write-enable pins; (12)Supports free-running 50% duty cycle clock inputs; (13)Width-expansion capability; (14)Pin-compatible 3.3 V solutions for CY7C4261/71/81/91; (15)Pin-compatible density upgrade to CY7C42X1V family; (16)Pb-free packages available.
Diagrams
| Image | Part No | Mfg | Description |  |
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 CY7C4291V-15JXC |
Cypress Semiconductor |
FIFO 128K X9 LO VLTG DEEP SYNC FIFO COM |
Data Sheet |
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